With the recent increase in the circuit size of devices including a processor or the like (hereinafter also referred to as chips), a test on chips during the design phase and one before shipment (hereinafter collectively referred to as a chip test) are imposing enormous costs.
There are a variety of techniques for chip tests, and a built-in self-test (BIST) is known as an example. The BIST is a technique for a chip test using a dedicated circuit (hereinafter referred to as a BIST circuit) that has a function of an LSI tester conducting a chip test and is incorporated into a chip. Examples of LSI tester functions are a function of generating a test pattern, a function of supplying the test pattern to the chip as an input signal, a function of obtaining an output signal of the chip, and a function of comparing the output signal with an expected value. As compared to the case of using only an LSI tester, the use of the BIST can cut the costs required for a chip test and increase the speed of the chip test. Patent Document 1 discloses a technique for achieving a BIST circuit provided outside LSI by using a field-programmable gate array (FPGA).